1. Field of the Invention
The present invention relates to an interconnection structure used in semiconductor elements, and more particularly to a multilayer interconnection structure.
2. Description of Related Art
FIG. 1 shows a typical constitution of an interconnection structure wherein the upper interconnection layer and lower interconnection layer are electrically connected through a via hole.
Referring to FIG. 1, the lower interconnection layer 102 is formed on a substrate 100. An interlayer insulating film 104 is formed on the upper surface of the substrate 100 so as to cover this lower interconnection layer 102. The upper interconnection layer 106 is formed on the interlayer insulating film 104. The via hole 108 is formed in the interlayer insulating film 104. The upper interconnection layer 106 and lower interconnection layer 102 are electrically connected through the via hole 108. The inner walls of the via hole 108 are generally covered with a barrier metal 110. For example, tungsten (W) 112 is laid on the surface of the barrier metal 110 and the interior of the hole 108.
The following structures are known as the upper interconnection layer 106 and lower interconnection layer 102 respectively: a two-layered structure of Al (aluminum) alloy layer and high melting point metal layer formed as a barrier metal which having a melting point higher than that of the Al alloy, or a three-layered structure of the Al alloy layer held between the high melting point metal layers. In the example shown in FIG. 1, the upper interconnection layer 106 and lower layer interconnection 102 are the three-layered structure. Consequently, the lower interconnection layer 102 has a structure wherein the Al alloy layer 116 is held between the high melting point metal layer 120a and 120b. The upper interconnection layer 106 has a structure wherein the Al alloy layer 114 is held between the high melting point metal layers 118a and 118b. 
The interconnection structure according to the present invention comprises an interlayer insulating film, first interconnection layer provided on one surface thereof and second interconnection layer on the other surface thereof. The interlayer insulating film has formed therethrough a via hole. Voltage is applied to the interconnection to become the first interconnection lower potential, the second interconnection higher potential. The first interconnection layer and second interconnection layer are established with the interlayer insulating film interposed therebetween and are electrically connected through the via hole.
An overlap region including the region facing (or in contact with) the via hole is formed in both the first interconnection and second interconnection layers. In other words, this overlap region is the region where the first interconnection and second interconnection layers overlap with the interlayer insulating film therebetween and the via hole is formed in the interlayer insulating film within this region.
A barrier metal is formed in the first interconnection layer and/or the second interconnection layer, in order to prevent from moving metal atoms between the interconnection layers. In this type of interconnection structure, the shortest distance from the edge of the via hole-faced (or contact) region of the overlap region of the first interconnection layer to the end of that interconnection is no more than 50 xcexcm and is longer than the shortest distance from the edge of the via hole contact region of the overlap region of the second interconnection layer to the end of that interconnection. The interconnection resistance of the first interconnection layer is greater than the interconnection layer resistance of the second interconnection layer.
When voltage is applied to this interconnection structure so that the first interconnection layer is at a low potential and the second interconnection layer is at a high potential, the amount of Joule heating due to the current flow is greater in the first interconnection layer than in the second interconnection layer within the range of the interconnection thickness used in ordinary LSI chips, because the interconnection resistance of the first interconnection layer is greater than that of the second interconnection layer. Accordingly, the temperature of the first interconnection layer becomes greater than that of the second interconnection layer. As a result, the temperature of the overlap region of both sets of interconnection layers (perimeter of the via hole-faced (or contact) region) becomes high temperature and the temperature in the region of the second interconnection layer (except overlap region) becomes low temperature. Consequently, the temperature gradient at the boundary between the overlap region and the second interconnection layer becomes large.
The migration velocity of the metal forming the interconnection (also called xe2x80x9cinterconnection metalxe2x80x9d) changes exponentially relative to the temperature. In the interconnection structure, the migration velocity in the overlap region (high temperature region) is high and the migration velocity in the region of the second interconnection layer (low temperature region) is low. Consequently, the migration velocity drops abruptly because of the large temperature gradient at the boundary between the overlap region and the second interconnection layer. Accordingly, the vicinity of the above-mentioned boundary, wherein the temperature gradient is large, becomes a barrier to migration. Effects which are substantially the same as backflow effects can thereby be attained with this barrier. Accordingly, the progression of voids, due to movement of the interconnection metal in the vicinity of the boundary, can be suppressed. Consequently, the EM resistance of this interconnection layer structure can be improved.
The shortest distance from the edge of the via hole contact region of the overlap region of the first interconnection layer to the end thereof is greater than the shortest distance from the edge of the via hole contact region of the overlap region of the second interconnection layer to the end thereof. As a result, heat generated in the first interconnection layer can be conducted efficiently to the second interconnection layer in the overlap region of the first and second interconnection layers. Since the shortest distance from the edge of the via hole contact region of the overlap region of the first interconnection layer to the end thereof is no more than 50 xcexcm, the boundary of the overlap region and the region of second interconnection layer only can be established at a position such that void progression can be suppressed at an early stage.